In recent years, the technology of thin film transistor panel is making progress continuously, which includes the driving circuit been integrated on panels. Such as the SOG (system on glass) technology can be actualized by technologies of a-Si (amorphous silicon) and LTPS (low temperature poly-silicon). The major difference between a LTPS TFT and an a-Si TFT is the complexity of the manufacturing process and the electrical characteristics. A LTPS TFT has a higher carrier-mobility whereas its manufacturing process is more complicated. By contrast, a-Si TFT has a lower carrier-mobility than LTPS, but its manufacturing process is simpler and well developed, and therefore an a-Si TFT has a better competitiveness in terms of cost.
However, due to the limit of manufacturing ability, the threshold voltage (Vth) for the manufactured a-Si TFT elements that follows the affection of the bias stress increases gradually. This is an important reason why a SOG panel cannot be actualized by an a-Si TFT. In the well known technologies, several amorphous silicon thin film transistors of a scanning shift circuit whose components are amorphous silicon thin film transistors have the problem of Vth shift. Along with the increasing operating time, the Vth shift severely affects the normal operation of the scanning shift circuit, even the scanning shift circuit will fail at last.
As is known to all, U.S. Pat. No. 6,690,347 entitled “SHIFT REGISTER AND LIQUID CRYSTAL DISPLAY USING THE SAME” (Feb. 10, 2004) proposed a scanning shift circuit. Please refer to FIGS. 6 and 7 that are the schematic diagram and the timing diagram for the shift register circuit of the patent respectively. As shown in FIG. 7, the bias voltage value for gate-source voltages (Vgs2, Vgs4) of transistors NT2 and NT4 are zero only in the two pulses time when the input terminal IN is at a high-level state (VDD) and when the output terminal OUT is at a high-level state (VDD). The bias voltage value for gate-source voltages (Vgs2, Vgs4) of transistors NT2 and NT4 are positive in the rest time. Consequently, severe threshold voltage shift for transistors NT2 and NT4 are caused due to the long-term positive bias, as shown in FIG. 8. The threshold voltages for transistors NT2 and NT4 rise gradually along with the operating time.
When severe threshold voltage shift for transistors NT2 and NT4 are caused, the value of the threshold voltage is much higher than the normal value, which results in the following problems:                1. When the output terminal OUT is kept at a low-level state (VSS), the impedance between the output terminal OUT and the power voltage VSS should be kept at low by way of turning on the transistor NT2 continuously. However, when the threshold voltage of transistor NT2 is increasing, the impedance between the output terminal OUT and the power voltage VSS is increasing at the same time. As a result, the output terminal OUT is easily affected by other signals or noises such that the output terminal OUT cannot be kept at a low-level state (VSS). Therefore, the scanning signal provided by the shift circuit will be distorted and then the driving for the display panel will be misacted.        2. When the output terminal OUT is kept at a low-level state (VSS), for avoiding the high-level signal (VDD) of the clock-pulse signal CK to affect the low-level signal (VSS) of the output terminal OUT through the transistor NT1, the node P1 should be kept at a low-level state (VSS) so as to assure that the transistor NT1 is at a cut-off state. Keeping the node P1 at a low-level state (VSS) is achieved by turning on the transistor NT4 continuously. However, when the threshold voltage of transistor NT4 is increasing, the impedance between the node P1 and the power voltage VSS is increasing at the same time. As a result, the node P1 is easily affected by other signals or noises such that the node P1 cannot be kept at a low-level state (VSS). Therefore, the high-level signal (VDD) of the clock-pulse signal CK may affect the low-level signal (VSS) of the output terminal OUT through the transistor NT1 so that the scanning signal provided by the shift circuit will be distorted and then the driving for the display panel will be misacted.        